Re: Use case


Antti Lukats
 

nice, that could be set as long term goal, but full 100% plug and play is not set as ultimate target, so it may take a while..

Some comments: when the carrier wakes up, then either SoC (if hard CPU part of main IC), or FPGA cold-boot image or baseboard controller would try to enumerate all detected modules. For some subset of modules this information maybe sufficient to generate the device tree, for all I2C, SPI like stuff and some more generic interfaces. For complex interfaces it gets more complicated as the FPGA "SoC" builder may have to pull in IP cores support different interfaces. Things that maybe possible are like generating the constraint files for the FPGA I/O connections and validating that the I/O banking and standard rules are OK, etc.

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